chandrusbyadgi

Tasks and
Functions
Programmable Logic Design (40-493)
Fall 2001
Computer Engineering Department
Sharif University of Technology
Maziar Gudarzi
Introductiion
Procedures/Subroutiines/Functiions iin
SW programmiing llanguages
The same functionality, in different places
Veriillog equiivallence:
Tasks and Functions
Used in behavioral modeling
Part of design hierarchy Hierarchical
name
Contents
Diifffferences between tasks and
ffunctiions
Tasks
Functiions
Differences
between Tasks and
Functions
Tasks and
Functions
Differences between......
Functions
Can enable (call) just
another function (not
task)
Execute in 0 simulation
time
No timing control
statements allowed
At lease one input
Return only a single value
Tasks
Can enable other tasks
and functions
May execute in non-zero
simulation time
May contain any timing
control statements
May have arbitrary input,
output, or inouts
Do not return any value
Diifffferences between… (cont’’d)
Both
are defined in a module
are local to the module
can have local variables (registers, but not nets)
and events
contain only behavioral statements
do not contain initial or always statements
are called from initial or always statements or
other tasks or functions
Diifffferences between… (cont’’d)
Tasks can be used for common Verilog code
Function are used when the common code
is purely combinational
executes in 0 simulation time
provides exactly one output
Functions are typically used for conversions
and commonly used calculations
Tasks
Tasks and
Functions
Tasks
Keywords: task, endtask
Must be used iiff the procedure has
any timing control constructs
zero or more than one output arguments
no input arguments
Tasks (cont’’d)
Task decllaratiion and iinvocatiion
Declaration syntax
task ;

begin // if more than one statement needed

end // if begin used!
endtask
Tasks (cont’’d)
Task decllaratiion and iinvocatiion
Task invocation syntax
;
();
input and inout arguments are passed into
the task
output and inout arguments are passed back
to the invoking statement when task is
completed
Tasks (cont’’d)
I/O decllaratiion iin modulles vs.. tasks
Both used keywords: input, output, inout
In modules, represent ports
connect to external signals
In tasks, represent arguments
pass values to and from the task
Task Examples
Use of input and output arguments
module operation;
parameter delay = 10;
reg [15:0] A, B;
reg [15:0] AB_AND, AB_OR, AB_XOR;
initial
$monitor( …);
initial
begin
…
end
always @(A or B)
begin
bitwise_oper(AB_AND, AB_OR,
AB_XOR, A, B);
end
task bitwise_oper;
output [15:0] ab_and, ab_or,
ab_xor;
input [15:0] a, b;
begin
#delay ab_and = a & b;
ab_or = a | b;
ab_xor = a ^ b;
end
endtask
endmodule
Task Examples
Use of module local variables
module sequence;
reg clock;
initial
begin
…
end
initial
init_sequence;
always
asymmetric_sequence;
task init_sequence;
begin
clock = 1'b0;
end
endtask
task asymmetric_sequence;
begin
#12 clock = 1'b0;
#5 clock = 1'b1;
#3 clock = 1'b0;
#10 clock = 1'b1;
end
endtask
endmodule
Functions
Tasks and
Functions
Functiions
Keyword: ffunctiion, endffunctiion
Can be used iiff the procedure
does not have any timing control constructs
returns exactly a single value
has at least one input argument
Functiions (cont’’d)
Functiion Decllaratiion and Invocatiion
Declaration syntax:
function ;

begin // if more than one statement needed

end // if begin used
endfunction
Functiions (cont’’d)
Functiion Decllaratiion and Invocatiion
Invocation syntax:
();
Functiions (cont’’d)
Semantiics
much like function in Pascal
An internal implicit reg is declared inside
the function with the same name
The return value is specified by setting that
implicit reg
defines width and type
of the implicit reg
type can be integer or real
default bit width is 1
Function Examples
Parity Generator
module parity;
reg [31:0] addr;
reg parity;
Initial begin
…
end
always @(addr)
begin
parity = calc_parity(addr);
$display("Parity calculated = %b",
calc_parity(addr) );
end
function calc_parity;
input [31:0] address;
begin
calc_parity = ^address;
end
endfunction
endmodule
Function Examples
Controllable Shifter
module shifter;
`define LEFT_SHIFT 1'b0
`define RIGHT_SHIFT 1'b1
reg [31:0] addr, left_addr,
right_addr;
reg control;
initial
begin
…
end
always @(addr)begin
left_addr =shift(addr, `LEFT_SHIFT);
right_addr =shift(addr,`RIGHT_SHIFT);
end
function [31:0] shift;
input [31:0] address;
input control;
begin
shift = (control==`LEFT_SHIFT)
?(address<<1)>>1);
end
endfunction
endmodule
Today Summary
Tasks and ffunctiions iin behaviiorall modelliing
The same purpose as subroutines in SW
Provide more readability, easier code
management
Are part of design hierarchy
Tasks are more general than functions
Can represent almost any common Verilog code
Functions can only model purely combinational
calculations